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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 14 1 publication order number: CS5303/d CS5303 three?phase buck controller with integrated gate drivers the CS5303 is a three ? phase step down controller which incorporates all control functions required to power high performance processors and high current power supplies. proprietary multi ? phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. enhanced v 2 ? control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. the CS5303 multi ? phase architecture reduces output voltage and input current ripple, allowing for a significant reduction in inductor values and a corresponding increase in inductor current slew rate. this approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost. features ? enhanced v 2 control method ? 5 ? bit dac with 1.0% accuracy ? adjustable output voltage positioning ? 6 on ? board gate drivers ? 200 khz to 800 khz operation set by resistor ? current sensed through buck inductors, sense resistors, or v ? s control ? hiccup mode current limit ? individual current limits for each phase ? on ? board current sense amplifiers ? 3.3 v, 1.0 ma reference output ? 5.0 v and/or 12 v operation ? on/off control (through comp pin) http://onsemi.com device package shipping ordering information CS5303gdw28 so ? 28l 27 units/rail CS5303gdwr28 so ? 28l 1000 tape & reel pin connections so ? 28l dw suffix case 751f a = assembly location wl, l = wafer lot yy, y = year ww, w = work week marking diagram 1 CS5303 awlyyww 28 1 28 1 28 gndl2 v id0 gate(h)2 cs ref v cch12 cs3 gate(h)1 cs2 gnd1 cs1 gate(l)1 v drp v ccll1 v fb r osc comp gate(l)2 v id1 v ccl23 v id2 gnd3 v id4 gate(l)3 v id3 gate(h)3 i lim v cch3 ref
CS5303 http://onsemi.com 2 CS5303 + + +5.0 v +12 v l4 300 nh d1 bat54s +12 v d2 bas16lt1 c1 1 f c3 1 f c2 1 f q1 c1 q7 q2 q3 c2 l2 470 nh q4 470 nh l1 q5 q6 q9 470 nh l3 c3 q8 c20 ? 24 5 820 f, 16 v c26 ? 39 14 1200 f, 10 v c40 ? 51 12 10 f c3 c5 r1 r2 2.80 k 1 k r7 20 k c9 0.1 f .01 f .01 f c7 r6 20 k .01 f c1 c2 c1 0.1 f 20 k r5 c6 r8 r9 20 k 2.8 k 1 f c11 1 nf c4 c12 1 nf r10 10 k r3 56.2 k v out v id4 v id3 v id2 v id1 v id0 6.65 k enable comp v fb v drp cs1 cs2 cs3 cs ref v id0 v id2 v id3 v id4 i lim ref v cch3 gate(h)3 gnd3 gate(l)3 gate(l)2 v ccl23 gate(h)2 gndl2 v cch12 gate(h)1 gnd1 gate(l)1 v ccll2 r osc v id1 note: q1 ? 9 are siliconix sud50n03 ? 10p. figure 1. application diagram, 12 v to 1.5 v, 60 a converter absolute maximum ratings* rating value unit operating junction temperature 150 c lead temperature soldering: : reflow: (smd styles only) (note 1) 230 peak, c storage temperature range ? 65 to +150 c esd susceptibility (human body model) 2.0 kv 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. absolute maximum ratings pin name pin symbol v max v min i source i sink power for logic and gate(l)1 v ccll1 16 v ? 0.3 v n/a 1.5 a, 1.0 s 200 ma dc power for gate(l)2 and gate(l)3 v ccl23 16 v ? 0.3 v n/a 1.5 a, 1.0 s 200 ma dc power for gate(h)1 and gate(h)2 v cch12 20 v ? 0.3 v n/a 1.5 a, 1.0 s 200 ma dc power gate(h)3 v cch3 20 v ? 0.3 v n/a 1.5 a, 1.0 s 200 ma dc
CS5303 http://onsemi.com 3 absolute maximum ratings (continued) pin name i sink i source v min v max pin symbol voltage feedback compensation network comp 6.0 v ? 0.3 v 1.0 ma 1.0 ma voltage feedback input v fb 6.0 v ? 0.3 v 1.0 ma 1.0 ma output for adjusting adaptive volt- age positioning v drp 6.0 v ? 0.3 v 1.0 ma 1.0 ma frequency resistor r osc 6.0 v ? 0.3 v 1.0 ma 1.0 ma reference output ref 6.0 v ? 0.3 v 1.0 ma 50 ma high ? side fet drivers gate(h)1 ? 3 20 v ? 0.3 v ? 2 v for 100 ns 1.5 a, 1.0 s 200 ma dc 1.5 a, 1 s 200 ma dc low ? side fet drivers gate(l)1 ? 3 16 v ? 0.3 v ? 2 v for 100 ns 1.5 a, 1.0 s 200 ma dc 1.5 a, 1.0 s 200 ma dc return for #1 driver gnd1 0.3 v ? 0.3 v 2 a, 1.0 s 200 ma dc n/a return for logic and #2 driver gndl2 n/a n/a 2.0 a, 1.0 s 200 ma dc n/a return for #3 driver gnd3 0.3 v ? 0.3 v 2.0 a, 1.0 s 200 ma dc n/a current sense for phases 1 ? 3 cs1 ? cs3 6.0 v ? 0.3 v 1.0 ma 1.0 ma current limit set point i lim 6.0 v ? 0.3 v 1.0 ma 1.0 ma current sense reference cs ref 6.0 v ? 0.3 v 1.0 ma 1.0 ma voltage id dac inputs vid0 ? 4 6.0 v ? 0.3 v 1.0 ma 1.0 ma electrical characteristics (0 c < t a < 70 c; 0 c < t j < 125 c; 4.7 v < v ccl < 14 v; 8 v < v cch < 20 v; c gate(h) = 3.3 nf, c gate(l) = 3.3 nf, r r(osc) = 53.6 k, c comp = 0.1 f, c ref = 0.1 f, dac code 10000, c vcc = 1.0 f, i lim 1 v; unless otherwise specified.) characteristic test conditions min typ max unit voltage identification dac (0 = connected to v ss ; 1 = open or pull ? up to 3.3 v) accuracy (all codes) measure v fb = comp 1.0 % v id4 v id3 v id2 v id1 v id0 1 1 1 1 1 ? 1.064 1.075 1.086 v 1 1 1 1 0 ? 1.089 1.100 1.111 v 1 1 1 0 1 ? 1.114 1.125 1.136 v 1 1 1 0 0 ? 1.139 1.150 1.162 v 1 1 0 1 1 ? 1.163 1.175 1.187 v 1 1 0 1 0 ? 1.188 1.200 1.212 v 1 1 0 0 1 ? 1.213 1.225 1.237 v 1 1 0 0 0 ? 1.238 1.250 1.263 v 1 0 1 1 1 ? 1.262 1.275 1.288 v 1 0 1 1 0 ? 1.287 1.300 1.313 v 1 0 1 0 1 ? 1.312 1.325 1.338 v 1 0 1 0 0 ? 1.337 1.350 1.364 v 1 0 0 1 1 ? 1.361 1.375 1.389 v 1 0 0 1 0 ? 1.386 1.400 1.414 v 1 0 0 0 1 ? 1.411 1.425 1.439 v 1 0 0 0 0 ? 1.436 1.450 1.465 v
CS5303 http://onsemi.com 4 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 4.7 v < v ccl < 14 v; 8 v < v cch < 20 v; c gate(h) = 3.3 nf, c gate(l) = 3.3 nf, r r(osc) = 53.6 k, c comp = 0.1 f, c ref = 0.1 f, dac code 10000, c vcc = 1.0 f, i lim 1 v; unless otherwise specified.) characteristic unit max typ min test conditions voltage identification dac (0 = connected to v ss ; 1 = open or pull ? up to 3.3 v) 0 1 1 1 1 ? 1.460 1.475 1.490 v 0 1 1 1 0 ? 1.485 1.500 1.515 v 0 1 1 0 1 ? 1.510 1.525 1.540 v 0 1 1 0 0 ? 1.535 1.550 1.566 v 0 1 0 1 1 ? 1.559 1.575 1.591 v 0 1 0 1 0 ? 1.584 1.600 1.616 v 0 1 0 0 1 ? 1.609 1.625 1.641 v 0 1 0 0 0 ? 1.634 1.650 1.667 v 0 0 1 1 1 ? 1.658 1.675 1.692 v 0 0 1 1 0 ? 1.683 1.700 1.717 v 0 0 1 0 1 ? 1.708 1.725 1.742 v 0 0 1 0 0 ? 1.733 1.750 1.768 v 0 0 0 1 1 ? 1.757 1.775 1.793 v 0 0 0 1 0 ? 1.782 1.800 1.818 v 0 0 0 0 1 ? 1.807 1.825 1.843 v 0 0 0 0 0 ? 1.832 1.850 1.869 v input threshold v id4 , v id3 , v id2 , v id1 , v id0 1.00 1.25 1.50 v input pull ? up resistance v id4 , v id3 , v id2 , v id1 , v id0 25 50 100 k pull ? up voltage ? 3.15 3.30 3.45 v voltage feedback error amplifier v fb bias current (note 2) 1.0 v < v fb < 1.9 v 16.8 19.0 21.5 a comp source current comp = 0.5 v to 2.0 v; v fb = 1.8 v; dac = 00000 15 30 60 a comp sink current comp = 0.5 v to 2.0 v; v fb = 1.9 v; dac = 00000 15 30 60 a comp discharge threshold voltage ? 0.20 0.27 0.34 v transconductance ? 10 a < i comp < +10 a ? 32 ? mmho output impedance ? ? 2.5 ? m open loop dc gain note 3 60 90 ? ? unity gain bandwidth 0.01 f comp capacitor ? 400 ? khz psrr @ 1 khz ? ? 70 ? db comp max voltage v fb = 1.8 v; comp open; dac = 00000 2.4 2.7 ? v comp min voltage v fb = 1.9 v; comp open; dac = 00000 ? 0.1 0.2 v hiccup latch discharge current ? 2.0 5.0 10 a comp discharge ratio ? 4.0 6.0 10 ? 2. the v fb bias current changes with the value of r osc per figure 4. 3. guaranteed by design. not tested in production.
CS5303 http://onsemi.com 5 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 4.7 v < v ccl < 14 v; 8 v < v cch < 20 v; c gate(h) = 3.3 nf, c gate(l) = 3.3 nf, r r(osc) = 53.6 k, c comp = 0.1 f, c ref = 0.1 f, dac code 10000, c vcc = 1.0 f, i lim 1 v;unless other- wise specified) characteristic test conditions min typ max unit pwm comparators minimum pulse width measured from csx to gate(h) v(v fb ) = v(cs ref ) = 1.0 v, v(comp) = 1.5 v 60 mv step applied between v csx and v cref ? 350 515 ns channel start up offset v(cs1) = v(cs2) = v(cs3) = v(v fb ) = 0.3 v(cs ref ) = 0 v; measure v(comp) when gate1(h), 2(h), 3(h) switch high 0.4 0.5 ? v gate(h) and gate(l) high voltage (ac) note 4 measure v cclx ? gate(l) or v cchx ? gate(h) ? 0 1.0 v low voltage (ac) note 4, measure gate(l) or gate(h) ? 0 0.5 v rise time gate(h)x 1.0 v < gate < 8.0 v; v cchx = 10 v ? 35 80 ns rise time gate(l)x 1.0 v < gate < 8.0 v; v cclx = 10 v ? 35 80 ns fall time gate(h)x 8.0 v > gate > 1.0 v; v cchx = 10 v ? 35 80 ns fall time gate(l) 8.0 v > gate > 1.0 v; v cclx = 10 v ? 35 80 ns gate(h) to gate(l) delay gate(h) < 2.0 v, gate(l) > 2 v 30 65 110 ns gate(l) to gate(h) delay gate(l) < 2.0 v, gate(h) > 2 v 30 65 110 ns gate pull ? down force 100 a into gate driver with no power applied to v cchx and v cclx = 2 v. ? 1.2 1.6 v oscillator switching frequency measure any phase (r osc = 53.6 k) 220 250 280 khz switching frequency note 4 measure any phase (r osc = 32.4 k) 300 400 500 khz switching frequency note 4 measure any phase (r osc = 16.2 k) 600 800 1000 khz r osc voltage ? ? 1.00 ? v phase delay ? 105 120 135 deg adaptive voltage positioning v drp output voltage to dac out offset cs1 = cs2 = cs3 = cs ref , v fb = comp measure v drp ? comp ? 20 ? 20 mv maximum v drp voltage |(cs1 = cs2 = cs3) ? c ref | = 50 mv, v fb = comp, measure v drp ? comp 360 465 570 mv current sense amp to v drp gain ? 2.4 3.0 3.8 v/v current sensing and sharing cs1 ? cs3 input bias current v(csx) = v(cs ref ) = 0 v ? 0.2 2.0 a cs ref input bias current ? ? 0.6 6.0 a current sense amplifiers gain ? 3.8 4.3 4.8 v/v current sense amp mismatch (the sum of offset and gain errors) note 4 0 (csx ? cs ref ) 50 mv ? 5.0 ? 5.0 mv current sense amplifiers input common mode range limit note 4 7 v < v ccll1 < 12 v 0 ? v ccll1 ? 2 v current sense input to i lim gain 0.25 v < i lim < 1.20 v 5.0 6.5 8.0 v/v current limit filter slew rate note 4 7.5 15.0 40.0 mv/ s 4. guaranteed by design. not tested in production.
CS5303 http://onsemi.com 6 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 4.7 v < v ccl < 14 v; 8 v < v cch < 20 v; c gate(h) = 3.3 nf, c gate(l) = 3.3 nf, r r(osc) = 53.6 k, c comp = 0.1 f, c ref = 0.1 f, dac code 10000, c vcc = 1.0 f, i lim 1 v;unless other- wise specified) characteristic unit max typ min test conditions current sensing and sharing i lim bias current 0 < i lim < 1.0 v ? 0.1 1.0 a single phase pulse by pulse current limit: v(csx) ? v(cs ref ) ? 60 70 90 mv current share amplifier bandwidth note 5 1.0 ? ? mhz reference output v ref output voltage 0 ma < i(v ref ) < 1.0 ma 3.15 3.25 3.35 v general electrical specifications v ccll1 operating current v fb = comp(no switching) ? 23 28 ma v ccl23 operating current v fb = comp(no switching) ? 8.0 11 ma v cch12 operating current v fb = comp(no switching) ? 5.5 7.0 ma v cch3 operating current v fb = comp(no switching) ? 2.5 3.5 ma v ccll1 start threshold gates switching, comp charging 4.05 4.40 4.70 v v ccll1 stop threshold gates stop switching, comp discharging 3.75 4.20 4.60 v v ccll1 hysteresis gates not switching, comp not charging 100 200 300 mv v cch12 start threshold gates switching, comp charging 1.7 1.9 2.1 v v cch12 stop threshold gates stop switching, comp discharging 1.55 1.75 1.90 v v cch12 hysteresis gates not switching, comp not charging 100 200 300 mv 5. guaranteed by design. not tested in production. package pin description package pin # pin symbol function 28 lead so wide 1 comp output of the error amplifier and input for the pwm comparators. 2 v fb voltage feedback pin. to use adaptive voltage positioning (avp) select an offset voltage at light load and connect a resistor between v fb and v out . the input bias current of the v fb pin and the resistor value determine output voltage off- set for zero output current. short v fb to v out for no avp. 3 v drp current sense output for avp. the offset of this pin above the dac voltage is proportional to the output current. connect a resistor from this pin to v fb to set amount avp or leave this pin open for no avp. 4 ? 6 cs1 ? cs3 current sense amplifier inputs. connect current sense net- work for the corresponding phase to each input. 7 cs ref reference for current sense amplifiers. to balance input offset voltages between the inverting and noninverting inputs of the current sense amplifiers, connect a resistor between cs ref and the output voltage. the value should be 1/3 of the value of the resistors connected to the csx pins. 8 ? 12 vid4 ? vid0 voltage id dac inputs. these pins are internally pulled up to 3.3 v if left open. 13 i lim sets threshold for current limit. connect to reference through a resistive divider.
CS5303 http://onsemi.com 7 package pin description (continued) package pin # function pin symbol 28 lead so wide function pin symbol 14 ref reference output. decouple with 0.1 f to gndl2 15 v cch3 power for gate(h)3. 16 gate(h)3 high side driver #3. 17 gnd3 return for #3 drivers. 18 gate(l)3 low side driver #3. 19 v ccl23 power for gate(l)2 and gate(l)3. 20 gate(l)2 low side driver #2. 21 gndl2 return for #2 driver, internal control circuits and ic substrate connection. 22 gate(h)2 high side driver #2. 23 v cch12 power for gate(h)1 and gate(h)2. uvlo sense for high side driver supply connects to this pin. 24 gate(h)1 high side driver #1. 25 gnd1 return for #1 drivers. 26 gate(l)1 low side driver #1. 27 v ccll1 power for internal control circuits and gate(l)1. uvlo sense for logic and low side driver supply connects to this pin. 28 r osc a resistor from this pin to ground sets operating frequency and v fb bias current.
CS5303 http://onsemi.com 8 ? + ? + ? + ? + ? + ? + ? ? + ? + ? + ? + + ? + ? + ? ? + ? + ? + ? + ? + ? + ? + ? co1 co1 ph 1 ph 2 ph 3 v ccll1 v cch12 v ccll1 3.3 v ref dac co1 dac out co2 co3 dac out fault co3 offset fault fault co2 co2 dac out fault ph 2 ph 3 ph 1 osc bias v cch12 v ccll1 v cch12 v ccl23 v cch3 v ccl23 v ccll1 v ccl23 v cch12 v cch3 i lim gate(h)1 gate(l)1 gnd1 gate(h)2 gate(l)2 gnd2 gate(h)3 gnd3 gate(l)3 s r r r s s r s fault 0.3 v 0.3 v 0.3 v 4.4 v 4.2 v 2 v 1.8 v comp discharge threshold v itotal v drp v fb comp r osc + current source gen gate nonoverlap reset dominant maxc1 maxc2 maxc3 pwmc1 pwmc2 pwmc3 ea 1 2 start stop csa1 csa2 csa3 + 5 a set dominant avpa 1.5 gate nonoverlap reset dominant gate nonoverlap reset dominant start stop ref v id0 v id1 v id2 v id3 v id4 cs1 cs2 cs3 c s ref 1 2 co3 fault figure 2. block diagram
CS5303 http://onsemi.com 9 typical performance characteristics 10 20 70 30 40 50 60 r osc value, k figure 3. oscillator frequency 900 800 700 600 500 400 300 200 100 frequency, khz 50 r osc value, k figure 4. v fb bias current vs. r osc value 0 v fb bias current, a 60 40 80 20 60 70 80 20 30 40 10 8 load capacitance, nf figure 5. gate(h) rise ? time vs. load capacitance measured from 1 v to 4 v with v cc at 5 v. 0 time, ns 60 40 80 20 10 12 14 24 6 0 100 120 16 8 load capacitance, nf figure 6. gate(l) rise ? time vs. load capacitance measured from 4 v to 1 v with v cc at 5 v. 0 time, ns 60 40 80 20 10 12 14 24 6 0 100 120 16 8 load capacitance, nf figure 7. gate(h) fall ? time vs. load capacitance measured from 4 v to 1 v with v cc at 5 v. 0 time, ns 60 40 80 20 10 12 14 24 6 0 100 120 16 8 load capacitance, nf figure 8. gate(l) fall ? time vs. load capacitance measured from 4 v to 1 v with v cc at 5 v. 0 time, ns 60 40 80 20 10 12 14 24 6 0 100 120 16
CS5303 http://onsemi.com 10 applications information fixed frequency multi ? phase control in a multi ? phase converter, multiple converters are connected in parallel and are switched on at different times. this reduces output current from the individual converters and increases the apparent ripple frequency. because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. the CS5303 uses a three ? phase, fixed frequency, enhanced v 2 architecture. each phase is delayed 120 from the previous phase. normally gate(h) transitions high at the beginning of each oscillator cycle. inductor current ramps up until the combination of the current sense signal and the output ripple trip the pwm comparator and bring gate(h) low. once gate(h) goes low, it will remain low until the beginning of the next oscillator cycle. while gate(h) is high, the enhanced v 2 loop will respond to line and load transients. once gate(h) is low, the loop will not respond again until the beginning of the next cycle. therefore, constant frequency enhanced v 2 will typically respond within the off ? time of the converter. the enhanced v 2 architecture measures and adjusts current in each phase. an additional input (c x ) for inductor current information has been added to the v 2 loop for each phase as shown in figure 9. figure 9. enhanced v 2 feedback and current sense scheme cs ref v out swnode c x v fb l r l r s comp dac out + + + + e.a. + + + + offset csa pwm- comp the inductor current is measured across r s , amplified by csa and summed with the offset and output voltage at the non ? inverting input of the pwm comparator. the inductor current provides the pwm ramp and as inductor current increases the voltage on the positive pin of the pwm comparator rises and terminates the pwm cycle. if the inductor starts the cycle with a higher current the pwm cycle will terminate earlier providing negative feedback. the CS5303 provides a c x input for each phase, but the cs ref , v fb and comp inputs are common to all phases. current sharing is accomplished by referencing all phases to the same v fb and comp pins, so that a phase with a larger current signal will turn off earlier than phases with a smaller current signal. including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. if the comp pin is held steady and the inductor current changes there must also be a change in the output voltage. or, in a closed loop configuration when the output current changes, the comp pin must move to keep the same output voltage. the required change in the output voltage or comp pin depends on the scaling of the current feedback signal and is calculated as v r s csa gain i the single ? phase power stage output impedance is; single stage impedance v i r s csa gain. the multi ? phase power stage output impedance is the single ? phase output impedance divided by the number of phases. the output impedance of the power stage determines how the converter will respond during the first few s of a transient before the feedback loop has repositioned the comp pin. the peak output current of each phase can also be calculated from; i pkout (per phase) v comp v fb v offset r s csa gain figure 10 shows the step response of a single phase with the comp pin at a fixed level. before t1 the converter is in normal steady state operation. the inductor current provides the pwm ramp through the current share amplifier. the pwm cycle ends when the sum of the current signal, voltage signal and offset exceed the level of the comp pin. at t1 the output current increases and the output voltage sags. the next pwm cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the v fb pin and the cycle ends at t2. after t2 the output voltage remains lower than at light load and the current signal level is raised so that the sum of the current and voltage signal is the same as with the original load. in a closed loop system the comp pin would move higher to restore the output voltage to the original level.
CS5303 http://onsemi.com 11 swnode v fb (v out ) csa out csa out + v fb figure 10. open loop operation comp ? offset t1 t2 inductive current sensing for lossless sensing current can be sensed across the inductor as shown below in figure 11. in the diagram l is the output inductance and r l is the inherent inductor resistance. to compensate the current sense signal the values of r1 and c1 are chosen so that l/r l = r1 c1. if this criteria is met the current sense signal will be the same shape as the inductor current, the voltage signal at cx will represent the instantaneous value of inductor current and the circuit can be analyzed as if a sense resistor of value r l was used as a sense resistor (r s ). s wnode v out dac out comp v fb cs ref cs csa offset pwm- comp e.a. r1 c1 l r l + + + + + + figure 11. lossless inductive current sensing with enhanced v 2 when choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. copper magnet wire has a temperature coefficient of 0.39% per c. the increase in winding resistance at higher temperatures should be considered when setting the i lim threshold. if a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in figure 9. current sharing accuracy pcb traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. for accurate current sharing, the current sense inputs should sense the current at the same point for each phase and the connection to the cs ref should be made so that no phase is favored. (in some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance.) the total current sense resistance used for calculations must include any pcb trace between the cs inputs and the cs ref input that carries inductor current. current sense amplifier input mismatch and the value of the current sense element will determine the accuracy of current sharing between phas es. the worst case current sense amplifier input mismatch is 5 mv and will typically be within 3 mv. the difference in peak currents between phases will be the csa input mismatch divided by the current sense resistance. if all current sense elements are of equal resistance a 3 mv mismatch with a 2 m sense resistance will produce a 1.5 a difference in current between phases. operation at > 50% duty cycle for operation at duty cycles above 50% enhanced v 2 will exhibit subharmonic oscillation unless a compensation ramp is added to each phase. a circuit like the one on the left side of figure 12 can be added to each current sense network to implement slope compensation. the value of r1 can be varied to adjust the ramp size. switch node cs x cs ref 25 k r1 .01 f 1 nf 0.1 f 3 k gate(l)x slope comp circuit existing current sense circuit mmbt2222lt1 figure 12. external slope compensation circuit
CS5303 http://onsemi.com 12 ramp size and current sensing because the current ramp is used for both the pwm ramp and to sense current, the inductor and sense resistor values will be constrained. a small ramp will provide a quick transient response by minimizing the difference over which the comp pin must travel between light and heavy loads, but a steady state ramp of 25 mv p ? p or greater is typically required to prevent pulse skipping and minimize pulse width jitter. for resistive current sensing the combination of the inductor and sense resistor values must be chosen to provide a large enough steady state ramp. for large inductor values the sense resistor value must also be increased. for inductive current sensing the rc network must meet the requirement of l/r l = r c to accurately sense the ac and dc components of the current the signal. again the values for l and r l will be constrained in order to provide a large enough steady state ramp with a compensated current sense signal. a smaller l, or a larger r l than optimum might be required. but unlike resistive sensing, with inductive sensing small adjustments can be made easily with the values of r and c to increase the ramp size if needed. if rc is chosen to be smaller (faster) than l/r l , the ac portion of the current sensing signal will be scaled larger than the dc portion. this will provide a larger steady state ramp, but circuit performance will be affected and must be evaluated carefully. the current signal will overshoot during transients and settle at the rate determined by r c. it will eventually settle to the correct dc level, but the error will decay with the time constant of r c. if this error is excessive it will effect transient response, adaptive positioning and current limit. during transients the comp pin will be required to overshoot along with the current signal in order to maintain the output voltage. the v drp pin will also overshoot during transients and possibly slow the response. single phase overcurrent will trip earlier than it would if compensated correctly and hiccup mode current limit will have a lower threshold for fast rise step loads than for slowly rising output currents. the waveforms in figure 13 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of l = 500 nh, r l = 1.6 m , r1 = 20 k and c1 = .01 f. for ideal current signal compensation the value of r1 should be 31 k . due to the faster than ideal rc time constant there is an overshoot of 50% and the overshoot decays with a 200 s time constant. with this compensation the i lim pin threshold must be set more than 50% above the full load current to avoid triggering hiccup mode during a large output load step. figure 13. inductive sensing waveform during a step with fast rc time constant (50 s/div) current limit two levels of overcurrent protection are provided. any time the voltage on a current sense pin exceeds cs ref by more than the single phase pulse by pulse current limit, the pwm comparator for that phase is turned off. this provides fast peak current protection for individual phases. the outputs of all the currents are also summed and filtered to compare an averaged current signal to the voltage on the i lim pin. if this voltage is exceeded, the fault latch trips and the ss capacitor is discharged by a 5 a source until the comp pin reaches 0.2 v. then soft ? start begins. the converter will continue to operate in this mode until the fault condition is corrected. overvoltage protection overvoltage protection (ovp) is provided as a result of the normal operation of the enhanced v 2 control topology with synchronous rectifiers. the control loop responds to an overvoltage condition within 400 ns, causing the top mosfet?s to shut off, and the synchronous mosfet?s to turn on. this results in a ?crowbar? action to clamp the output voltage and prevents damage to the load. the regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. transient response and adaptive positioning for applications with fast transient currents the output filter is frequently sized larger than ripple currents require in
CS5303 http://onsemi.com 13 order to reduce voltage excursions during transients. adaptive voltage positioning can reduce peak ? peak output voltage deviations during load transients and allow for a smaller output filter. the output voltage can be set higher at light loads to reduce output voltage sag when the load current is stepped up and set lower during heavy loads to reduce overshoot when the load current is stepped up. for low current applications a droop resistor can provide fast accurate adaptive positioning. however at high currents, the loss in a droop resistor becomes excessive. for example; in a 50 a converter a 1 m resistor to provide a 50 mv change in output voltage between no load and full load would dissipate 2.5 watts. lossless adaptive positioning is an alternative to using a droop resistor, but must respond quickly to changes in load current. figure 14 shows how adaptive positioning works. the waveform labeled normal shows a converter without adaptive positioning. on the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. with fast (ideal) adaptive positioning the peak to peak excursions are cut in half. in the slow adaptive positioning waveform the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. adaptive positioning adaptive positioning normal fast slow limits figure 14. adaptive positioning the CS5303 uses two methods to provide fast and accurate adaptive positioning. for low frequency positioning the v fb and v drp pins are used to adjust the output voltage with varying load currents. for high frequency positioning, the current sense input pins can be used to control the power stage output impedance. the transition between fast and slow positioning is adjusted by the error amp compensation. the CS5303 can be configured to adjust the output voltage based on the output current of the converter. the adaptive positioning circuit is designed to select the dac setting as the maximum output voltage. (refer to application diagram on page 2.) to set the no ? load positioning a resistor (r9) is placed between the output voltage and v fb pin. the v fb bias current will develop a voltage across the resistor to decrease the output voltage. the v fb bias current is dependent on the value of rosc. see figure 4 on the datasheet. during no load conditions the v drp pin is at the same voltage as the v fb pin, so none of the v fb bias current flows through the v drp resistor (r8). when output current increases the v drp pin increases proportionally and the v drp pin current offsets the v fb bias current and causes the output voltage to further decrease. the v fb and v drp pins take care of the slower and dc voltage positioning. the first few s are controlled primarily by the esr and esl of the output filter. the transition between fast and slow positioning is controlled by the ramp size and the error amp compensation. if the ramp size is too large or the error amp too slow there will be a long transition to the final voltage after a transient. this will be most apparent with lower capacitance output filters. note: large levels of adaptive positioning can cause pulse width jitter. error amp compensation the transconductance error amplifier can be configured to provide both a slow soft ? start and a fast transient response. c4 in the main applications diagram controls soft ? start. a 0.1 f capacitor with the 30 a error amplifier output capability will allow the output to ramp up at 0.3 v/ms or 1.5 v in 5 ms. r10 is connected in series with c4 to allow the error amplifier to slew quickly over a narrow range during load transients. here the 30 a error amplifier output capability works against 10 k (r10) to limit the window of fast slewing too 300 mv ? enough to allow for fast transients, but not enough to interfere with soft ? start. this window will be noticeable as a step in the comp pin voltage at start ? up. the size of this step must be kept smaller than the channel start ? up offset (nominally 0.4 v) for proper soft ? start operation. if adaptive positioning is used the r9 and r8 form a divider with the v drp end held at the dac voltage during start ? up, which effectively makes the channel start ? up offset larger. c12 is included for error amp stability. a capacitive load is required on the error amp output. use of values less than 1 nf may result in error amp oscillation of several mhz. c11 and the parallel resistance of the v fb resistor (r9) and the v drp resistor (r8) are used to roll off the error amp gain. the gain is rolled off at a high enough frequency to give a quick transient response, but low enough to cross zero db well below the switching frequency to minimize ripple and noise on the comp pin. uvlo the CS5303 has undervoltage lockout functions connected to two pins. one intended for the logic and low ? side drivers with a 4.4 v turn ? on threshold is connected to the v ccll1 pin. a second for the high side drivers has a 2 v threshold and is connected to the v cch12 pin. the uvlo threshold for the high side drivers was chosen at a low value to allow for flexibility in the part and an input voltage as low as 3.3 v. in many applications this will be
CS5303 http://onsemi.com 14 disabled or will only check that the applicable supply is on ? not that it is at a high enough voltage to run the converter. for the 12 v in converter in the application diagram on page 2 the uvlo pin for the high side driver is pulled up by the 5 v supply (through two diode drops) and the function is not used. the diode between the comp pin and the 12 v supply holds the comp pin near gnd and prevents start ? up while the 12 v supply is off. in an application where a higher uvlo threshold is necessary a circuit like the one in figure 15 will lock out the converter until the 12 v supply exceeds 9 v. figure 15. external uvlo circuit comp 100 k 100 k 50 k +5 v +12 v layout guidelines with the fast rise, high output currents of microprocessor applications parasitic inductance and resistance should be considered when laying out the power, filter and feedback signal sections of the board. typically a multi ? layer board with at least one ground plane is recommended. if the layout is such that high currents can exist in the ground plane underneath the controller or control circuitry, the ground plane can be slotted to reroute the currents away from the controller. the slots should typically not be placed between the controller and the output voltage or in the return path of the gate drive. additional power and ground planes or islands can be added as required for a particular layout. output filter components should be placed on wide planes connected directly to the load to minimize resistive drops during heavy loads and inductive drops and ringing during transients. if required, the planes for the output voltage and return can be interleaved to minimize inductance between the filter and load. voltage feedback should be taken from a point of the output or the output filter that doesn?t favor any one phase. if the feedback connection is closer to one inductor than the others the ripple associated with that phase may appear larger than the ripple associated with the other phases and poor current sharing can result. the current sense signal is typically tens of milli ? volts. noise pick ? up should be avoided wherever possible. current feedback traces should be routed away from noisy areas such as switch nodes and gate drive signals. the paths should be matched as well as possible. it is especially important that all current sense signals be picked off at similar points for accurate current sharing. if the current signal is taken from a place other than directly at the inductor any additional resistance between the pick ? off point and the inductor appears as part of the inherent inductor resistance and should be considered in design calculations. capacitors for the current feedback networks should be placed as close to the current sense pins as practical. design procedure current sensing, power stage and output filter components 1. choose the output filter components to meet peak transient requirements. the formula below can be used to provide an approximate starting point for capacitor choice, but will be inadequate to calculate actual values. v peak ( i t) esl i esr ideally the output filter should be simulated with models including esr, esl, circuit board parasitics and delays due to switching frequency and converter response. typically both bulk capacitance (electrolytic, oscon, etc,) and low impedance capacitance (ceramic chip) will be required. the bulk capacitance provides ?hold up? during the converter response. the low impedance capacitance reduces steady state ripple and bypasses the bulk capacitance during slewing of output current. 2. for inductive current sensing (only) choose the current sense network rc to provide a 25 mv minimum ramp during steady state operation. r (v in v out ) v out v in f c 25 mv then choose the inductor value and inherent resistance to satisfy l/r l = r c. for ideal current sense compensation the ratio of l and r l is fixed, so the values of l and r l will be a compromise typically with the maximum value r l limited by conduction losses or inductor temperature rise and the minimum value of l limited by ripple current. 3. for resistive current sensing choose l and r s to provide a steady state ramp greater than 25 mv. l r s (v in v out ) t on 25 mv again the ratio of l and r l is fixed and the values of l and r s will be a compromise. 4. calculate the high frequency output impedance (converterz) of the converter during transients. this is the impedance of the output filter esr in parallel with the power stage output impedance (pwrstgz) and will indicate how far from the original level ( vr) the output voltage will typically recover to within one switching cycle. for a good transient response vr should be less than the peak output voltage overshoot or undershoot.
CS5303 http://onsemi.com 15 vr converterz esr converterz pwrstgz esr pwrstgz esr where: pwrstgz r s csa gain 3 multiply the converterz by the output current step size to calculate where the output voltage should recover to within the first switching cycle after a transient. if the converterz is higher than the value required to recover to where the adaptive positioning is set the remainder of the recovery will be controlled by the error amp compensation and will typically recover in 10 ? 20 s. vr i out converterz make sure that vr is less than the expected peak transient for a good transient response. 5. adjust l and r l or r s as required to meet the best combination of transient response, steady state output voltage ripple and pulse width jitter. current limit when the sum of the current sense amplifiers (v itotal ) exceeds the voltage on the i lim pin the part will enter hiccup mode. for inductive sensing the i lim pin voltage should be set based on the inductor resistance (or current sense resistor) at max temperature and max current. to set the level of the i lim pin: 6. v i(lim) r i out(lim) cs to i lim gain where: r is r l or r s; i out(lim) is the current limit threshold. for the overcurrent to work properly the inductor time constant (l/r) should be the current sense rc. if the rc is too fast, during step loads the current waveform w ill appear larger than it is (typically for a few hundred s) and may trip the current limit at a level lower than the dc limit. adaptive positioning 7. to set the amount of voltage positioning below the dac setting at no load connect a resistor (r v ( fb )) between the output voltage and the v fb pin. choose r v ( fb ) as: r v(fb) nl position v fb bias current see figure 4 for v fb bias current. 8. to set the difference in output voltage between no load and full load, connect a resistor (r v(drp) ) between the v drp and v fb pins. r v(drp) can be calculated in two steps. first calculate the difference between the v drp and v fb pin at full load. (the v fb voltage should be the same as the dac voltage during closed loop operation.) then choose the r v(drp) to source enough current across r v ( fb ) for the desired change in output voltage. v v(drp) i outfl r cs to v drp gain where: r = r l or r s for one phase; i outfl is the full load output current. r v(drp) v drp r v(fb) v out design example choose the component values for lossless current sensing, adaptive positioning and current limit for a 60 a converter. the adaptive positioning is chosen 50 mv below the maximum v out at no load and 50 mv below the no ? load position with 60 a out. the peak output voltage transient is 100 mv max during a 60 a step current. the overcurrent limit is nominally 75 a. current sensing, power stage and output filter components 1. assume 1.5 m of output filter esr. r (v in v out ) (v out v in) (f c 25 mv) (12 1.5) (1.5 12) (250 k .01 f 25 mv) 21 k choose 20 k l r l .01 f 20 k 200 s choose r l 2m l 2m 200 s 400 nh 2. 3. n/a pwrstgz r l csa gain 3 1.5 m 4.2 3 2.1 m converterz pwrstgz esr pwrstgz esr 2.8 m 1.5 m 2.8 m 1.5 m 1m vr 1.2 m 60 a 60 mv 4.
CS5303 http://onsemi.com 16 5. n/a current limit v i(lim) r l i out(lim) cs to i lim gain 1.5 m 75 a 6.5 731 mv 6. adaptive positioning r v(fb) nl position v fb bias current 50 mv 19 a 2.63 k 7. v drp r l i out current sense to v drp gain 2m 60 a 3 360 mv r v(drp) v drp r v(fb) v out 360 mv 2.63 k 50 mv 18.9 k 8.
CS5303 http://onsemi.com 17 additional application diagrams + + figure 16. 5 v only to 1.2 v v id4 v id3 v id2 v id1 v id0 enable +5.0 v +5.0 v v out c3 c2 c1 c3 c2 c1 comp v fb cs1 cs2 cs3 v id0 v id3 i lim ref v cch3 gate(h)3 gnd3 gate(l)3 gate(l)2 v ccl23 gate(h)2 gndl2 v cch12 gate(h)1 gnd1 gate(l)1 v ccll2 r osc v id1 v drp cs ref v id4 v id2 u1 CS5303 + + v id4 v id3 v id2 v id1 v id0 comp v fb cs1 cs2 cs3 v id0 v id3 i lim ref v cch3 gate(h)3 gnd3 gate(l)3 gate(l)2 v ccl23 gate(h)2 gndl2 v cch12 gate(h)1 gnd1 gate(l)1 v ccll2 r osc v id1 v drp cs ref v id4 enable +12 v +12 v+5.0 v +12 v v out c3 c2 c1 c3 c2 c1 v id2 figure 17. 5 v to 1.2 v with 12 v bias u1 CS5303
CS5303 http://onsemi.com 18 additional application diagrams CS5303 + + +5 v +5 v c1 c2 c3 c1 c2 c3 enable r osc comp v fb v drp cs1 cs2 cs3 cs ref v id0 v id1 v id2 v id3 v id4 i lim ref v ccll1 gate(l)1 gate(h)1 gate(h)2 gate(l)2 gnd1 v cch12 gndl2 v ccl23 gate(l)3 gnd3 gate(h)3 v cch3 v out u1 figure 18. 5 v only to 2.5 v
CS5303 http://onsemi.com 19 package dimensions a1 1 15 14 28 b s a m 0.025 b s c m 0.25 b m seating plane a notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusions. 4. maximum mold protrusion 0.015 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 l 0.41 0.90 0 8 l c pin 1 ident a b d e h e 0.10 c so ? 28l dw suffix case 751f ? 05 issue f package thermal data parameter 28 lead so wide unit r jc typical 15 c/w r ja typical 75 c/w on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 CS5303/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative v 2 is a trademark of switch power, inc.

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